The present application is based on Japanese priority application No.2001-201055 filed on Jul. 2, 2001, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to semiconductor devices. Especially it is related to a non-volatile semiconductor memory device.
A non-volatile semiconductor memory device is a semiconductor memory device capable of holding information over long time period even if the supply of electric power is turned off. EEPROMs and flash memory devices are typical examples.
In these semiconductor memory devices, information is held in a floating gate electrode in the form of electric charges. Especially, as for a flash memory device, the cell area is small and it is suited to construct a large scale integrated circuit together with other semiconductor devices, especially logic semiconductor devices.
A typical conventional flash memory device has the floating gate electrode formed on a channel region via an intervening tunneling oxide film. Furthermore, a control electrode is formed on the floating gate electrode via an insulation film.
However, the flash memory device having such a stacked electrode structure has a problem in that the fabrication process thereof is complex.
On the other hand, a flash memory device having a single-layer gate structure is proposed in a related art of the present invention.
FIG. 1A is a plan view showing the construction of a flash memory device 10 according to such a related art, while FIGS. 1B and 1C show the cross-sectional view taken along a A-Axe2x80x2 line and B-Bxe2x80x2 line of FIG. 1A.
Referring to FIGS. 1A-1C, an active region 11A is defined by a field oxide film 11F formed on a Si substrate 11, and another active region 11B including a buried diffusion region 11Bu is defined in the vicinity of the active region 11A so as to extend parallel to the active region 11A. Further, diffusion regions 11a and 11b of n+-type are formed inside the active region 11A as shown in the cross-sectional view of FIG. 1B.
On the Si substrate 11, a gate electrode 13G is formed via a gate oxide film 12G at the part located between the diffusion regions 11a and 11b. By providing the gate electrode 13G, there is formed a MOS transistor having a channel region between the diffusion regions 11a and 11b in the active region 11A. This MOS transistor is used for reading the information.
Furthermore a different n+-type diffusion region 11c is formed in the vicinity of the diffusion region 11b inside the active region 11A at the opposite side of the diffusion region 11a, as shown in the cross-sectional view of FIG. 1B. Between the diffusion regions 11b and 11c, there is formed a floating gate electrode 13FG via a tunneling oxide film 12Tox. Further, an LDD region 11d of n-type is formed in a part of the diffusion region 11b at the side facing to the diffusion region 11c. 
Referring to the cross-sectional view of FIG. 1C, the floating gate electrode 13FG on the gate oxide film 12G extends over the field oxide film 11F toward the active region 11B, wherein the floating gate electrode 13FG extends further over the gate oxide film 12G covering the surface of Si substrate 11 in the active region 11B.
FIGS. 2A and 2B show the writing operation of the flash memory device 10 of FIGS. 1A-1C.
Referring to FIGS. 2A and 2B, the diffusion region 11b is grounded and a positive voltage of +5-+10V is applied to the diffusion region 11c at the time of writing. Thereby, hot electrons are formed in the vicinity of the diffusion region 11c. 
Simultaneously, a positive writing voltage of +15-20V is applied to the buried diffusion region 12Bu in the active region 11B. With this, the potential of the floating gate electrode 13Fg, which is capacitance-coupled to the buried diffusion region 12Bu, is lowered via the gate insulation film 12G. As a result, there occurs injection of the hot electrons into the floating gate electrode 13Fg in the active region 11A, and the electrons thus injected are held stability in the floating gate electrode 13Fg.
FIGS. 3A and 3B show the erasing operation of flash memory device 10 of FIGS. 1A-1C.
Referring to FIGS. 3A and 3B, the diffusion region 11c is set to a floating state at the time of the erasing operation of the flash memory device and a positive erasing voltage of +15-+20V is applied to the diffusion region 11b. As a result, the potential of the diffusion region 11b is lowered and the electrons accumulated in the floating gate electrode 13Fg are pulled out to the diffusion regions 11d and 11b through the tunneling insulation film 12Tox.
Thus, the flash memory device 10 of FIGS. 1A-1C has a desirable characteristic in that the production of the device is easy due to the single-layer structure of the gate electrode.
On the other hand, as will be understood from the plane view of FIG. 1A, the flash memory device 10 has a problem in that the memory cell area tends to become large due to the use of two gate electrodes, the selection gate electrode 13G and the floating gate electrode 13Fg, at the time of reading.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and the fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a flash memory device of single-layer gate structure that can reduce the memory cell area.
Another object of the present invention is to provide a non-volatile semiconductor memory device, comprising:
a p-type Si substrate;
an n-type well formed in said Si substrate;
a control gate formed of a p-type buried diffusion region formed in said n-type well;
an active region formed in said Si substrate in the vicinity of said n-type well, said active region being covered by a tunneling insulation film; and
a floating gate electrode formed on a surface of said Si substrate so as to achieve a capacitance coupling with said p-type buried diffusion region,
said floating gate electrode extending over said active region in a state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate,
said active region including a pair of n-type diffusion regions at both sides of said floating gate electrode respectively as a source region and a drain region,
said n-type diffusion region forming said source region having an nxe2x88x92-type diffusion region at the side facing said n-type diffusion region forming said drain region.
Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:
a p-type Si substrate;
a plurality of n-type wells formed repeatedly on said Si substrate, each of said n-type wells extending in said Si substrate in a first direction;
a control gate formed of a p-type buried diffusion region, said p-type buried diffusion region being formed in each of said n-type wells so as to extend in said first direction;
a plurality of active regions formed on said Si substrate between a pair of adjacent n-type wells, each of said active regions extending in said first direction and being covered with a tunneling insulation film;
a floating gate electrode provided on each of said n-type wells so as to achieve a capacitance coupling with said p-type buried diffusion region in said n-type well via an insulation film covering said surface of said Si substrate, said floating gate electrode extending over an active region adjacent to n-type well;
n-type diffusion regions formed at both sides of said floating gate electrode in each of said active regions;
a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, said bit lines making a contact with corresponding n-type diffusion regions in each of said active regions; and
a plurality of word lines respectively extending over said Si substrate in said first direction in correspondence said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.
Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:
a p-type Si substrate;
a plurality of n-type wells formed on said Si substrate repeatedly, each of said n-type wells extending in said Si substrate in a first direction;
a pair of buried diffusion regions formed in each of said n-type wells so as to extend in said first direction, each of said pair of buried diffusion regions forming a control gate;
a pair of active region formed on a surface of said Si substrate in a part located between a pair of neighboring n-type wells, each of said active regions extending in said first direction and being covered with a tunneling insulation film;
a floating gate electrode provided on each of said n-type wells so as to achieve a capacitance coupling with one of said p-type buried diffusion regions in said n-type well via an insulation film covering said surface of said Si substrate, said floating gate electrode extending over said active region adjacent to said n-type well;
a pair of n-type diffusion regions formed in each of said active regions at both sides of said floating gate electrode;
a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with a corresponding n-type diffusion region in each of said active regions; and
a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.
Another object of the present invention is to provide a non-volatile semiconductor device, comprising:
a p-type Si substrate;
an n-type buried diffusion region formed in said Si substrate as a control gate;
an active region formed in said Si substrate in the vicinity of said n-type buried diffusion region, said active region being covered by a tunneling insulation film; and
a floating gate electrode formed over a surface of said Si substrate so as to make a capacitance coupling with said n-type buried diffusion region via an insulation film;
said active region including a triple-well structure formed of said p-type Si substrate, an n-type well formed in said Si substrate and a p-type well formed in said n-type well,
said floating gate electrode extending over said active region in the state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate,
said Si substrate including a pair of n-type diffusion regions in said p-type well at both sides of said floating gate electrode respectively as a source region and a drain region.
Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:
a p-type Si substrate;
a plurality of n-type buried diffusion regions formed on said Si substrate repeatedly, each of said n-type buried diffusion regions extending in a first direction and forming a control gate;
a triple-well structure formed on said Si substrate between a pair of neighboring n-type buried diffusion regions, said triple-well structure including said p-type substrate, an n-type well formed in said p-type Si substrate, and a p-type well formed in said n-type well;
an active region extending in said p-type well in said first direction, said active region being covered with a tunneling insulation film;
a floating gate electrode provided on said Si substrate so as to achieve a capacitance coupling with said n-type buried diffusion region via an insulation film covering a surface of said Si substrate, said floating gate electrode extending over an active region adjacent to said n-type buried diffusion region;
a pair of n-type diffusion regions formed in each of said active regions at both lateral sides of said floating gate electrode;
a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with an n-type diffusion region in each of said plurality of active regions; and
a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a control gate in a corresponding n-type well.
Another object of the present invention is to provide a semiconductor integrated circuit device having a non-volatile memory cell array, comprising:
a p-type Si substrate;
a plurality of n-type buried diffusion regions formed on said Si substrate repeatedly in said first direction as a control gate;
a triple-well structure formed in a part of said Si substrate located between a pair of neighboring n-type buried diffusion regions and another pair of neighboring n-type buried diffusion regions, said triple-well structure including said p-type Si substrate, an n-type well formed in said Si substrate and a p-type well formed in said n-type well;
a pair of active regions extending in said first direction in said p-type well, each of said active regions being covered with a tunneling insulation film;
a floating gate electrode provided on said Si substrate so as to achieve a capacitance coupling with said n-type buried diffusion region via an insulation film covering a surface of said Si substrate, said floating gate electrode extending over said active region adjacent to said n-type buried diffusion region;
a pair of n-type diffusion regions formed in each of said active regions at both sides of said floating gate electrode;
a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said plurality of active regions, each of said bit lines making a contact with said n-type diffusion region in said active regions; and
a plurality of word lines extending over said Si substrate in said first direction respectively in correspondence to said plurality of n-type wells, each of said word lines making a contact with a corresponding control gate in said n-type wells.
Another object of the present invention is to provide a NAND-type non-volatile semiconductor memory device, comprising:
a p-type Si substrate;
a plurality of triple well structures each formed in said p-type Si substrate repeatedly, each of said triple well structures comprising said p-type Si substrate, an n-type well formed in said Si substrate so as to extend in said fist direction and a p-type well formed in said n-type well formed in said n-type well so as to extend in said first direction;
an active region formed in said p-type well in each of said plurality of triple well structures, said active region being covered with a tunneling insulation film;
a plurality of buried diffusion regions formed in said Si substrate in the vicinity of each of said triple well structures, each of said buried diffusion regions extending in said first direction and being aligned with each other in said first direction, said buried diffusion regions being further repeated in a second direction different from said first direction;
a plurality of floating gate electrodes each provided on said Si substrate so as to extend over a part thereof located between a buried diffusion region and a neighboring active region so as to achieve a capacitance coupling with said buried diffusion region via an insulation film formed on a surface of said Si substrate, said plurality of diffusion regions extending over said tunneling insulation film on said active region; and
a plurality of word lines extending over said Si substrate in a second direction across said plurality of triple well structures and said buried diffusion regions that are repeated in said second direction, each of said word lines making a contact with a buried diffusion region which is crossed with said word line,
said floating gate electrode being repeated in said first direction in correspondence to said plurality of buried diffusion regions aligned in said first direction, said floating gate electrode being further repeated in said second direction,
said plurality of word lines being repeated in said first direction.
Another object of the present invention is to provide a NAND-type non-volatile semiconductor memory device, comprising:
a p-type Si substrate;
a plurality of triple well structures formed in said p-type Si substrate repeatedly, each of said triple well structures comprising a part of said p-type Si substrate and an n-type well formed in said Si substrate so as to extend in said first direction and a p-type well formed in said n-type well in said first direction;
a pair of active regions formed in each of said plurality of triple well structures in said p-type well, each of said active regions extending in said fist direction and covered with a tunneling oxide film;
a plurality of buried diffusion regions each formed on said Si substrate in the vicinity of one of said triple well structures, each of said buried diffusion regions extending in said first direction and arranged in said first direction in two rows; and
a plurality of floating gate electrodes provided on said Si substrate so as to extend between each buried diffusion region and an active region neighboring thereto, each of said floating gate electrodes extending on said active region over said tunneling oxide film and making a capacitance coupling with said buried diffusion region via an insulation film formed on a surface of said Si substrate,
said plurality of triple well structures and said two rows of buried diffusion regions forming respectively a first structural unit and a second structural unit repeated over a surface of said Si substrate alternately in a second direction different from said first direction,
said non-volatile semiconductor memory device further having a plurality of word lines extending over said Si substrate in said second direction across said plurality of triple well structures and said buried diffusion regions that are repeated in said second direction, each of said word lines making a contact with a buried diffusion region each time said word line crosses a buried diffusion region;
said floating gate electrode being formed repeatedly in said first direction in correspondence to said plurality of buried diffusion regions aligned in said first direction,
said plurality of word lines being repeated in said first direction.
According to the present invention, it is no longer necessary to form the select gate for each memory cell in the flash memory device of the single-layer gate structure, and it becomes possible to reduce the memory cell area by about 50%. By integrating such flash memory devices having a reduced cell area with each other, it becomes possible to construct a highly integrated flash-memory integrated circuit device. Furthermore, it becomes possible to reduce the operational voltage at the time of wiring or erasing of the flash memory device. Furthermore, it becomes possible to reduce the cost of constructing a hybrid integrated circuit device in which a flash memory device is integrated together with other devices such as a logic circuit device.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.